Deposited magnetic memory array



Nov. 24, 1970 5, CHAPMAN ETAL Re. 26,983

nnrosn'nn menmrc MEMORY ARRAY Original Filed May 21, 1959 3 Sheets-Sheet1 [WE/ MR5 KENNETH F GREENE BRUNO J. RON KESE EDWARD B. CHAPMAN Aim/WE)NOV. 24, 1970 CHAPMAN ETAL Re. 26,983

DEPOSITED MAGNETIC MEMORY ARRAY Original Filed May 21, 1959 3Sheets-Sheet 8 FIG. 4

FIG.5

NOV. 24, 1970 5, CHAPMAN ETAL Re. 26,983

DEPOSITED MAGNETIC MEMORY ARRAY Original Filed May 21, 1959 3Sheets-Sheet S EPOXY com ,vAc DEPOSIT United States Patent Office Re.26,983 Reissued Nov. 24, 1970 26,983 DEPOSITED MAGNETIC MEMORY ARRAYEdward B. Chapman, Poughkeepsie, Kenneth F. Greene,

Woodstock, and Bruno J. Ronkese, Marlboro, N.Y.,

assignors to International Business Machines Corporation, New York,N.Y., a corporation of New York Original No. 3,138,785, dated June 23,1964, Ser. No.

814,772, May 21, 1959. Application for reissue June 21,

1965, Ser. No. 469,965

Int. Cl. Gllc 5/02, 11/14; Htllf 3/04 US. Cl. 340-474 11 Claims Matterenclosed in heavy brackets appears in the original patent but forms nopart of this reissue specification; matter printed in italics indicatesthe additions made by reissue.

ABSTRACT OF THE DISCLOSURE A flat noncondnctive substrate comprises agrid of separate memory areas formed by rows and columns of closelyspaced pairs of slot openings, there being provided between each pair ofopenings a separate memory area strip receptive to cylindrical deposits.A plurality of sets of printed conductors are provided on the substratewith conductors of difierent sets being grouped over each of the stripsin a memory area. There are further included cylindrical thin films ofmagnetic material deposited on the separate strips over the conductorsas separate memory elements, the material being of a nature whichexhibits square loop hysteresis characteristics.

This invention relates generally to the production of a magnetic memorycore element by an electroplating process and more particularly to thesimultaneous plating of a whole array or matrix of magnetic storageelements directly on a printed circuit board bearing conductor lines andterminals for supplying electrical current and pulses for driving,switching and reading the cores with associated windings such as write,inhibit and sense windings.

Heretofore, the core windings or conductor lines were in the form ofwires, and the cores were shaped as separate toroidal elementsnecessitating a tedious and complicated manual or mechanical threadingoperation. A core array often involved thousands of tiny cores and wirethreading of such small and fragile devices became costly no matter howskillfully or automatically the wire insertion was performed. NOW it isproposed that both wires and cores no longer be constructed or used asseparate elements, but instead, a substitute for the wires is to beprovided in the form of printed circuit lines which are formed rapidlyin quantities and in the proper close and modular formation to receivecores, and then also all the cores are to be plated in place all over aboard and directly around the previously formed windings so that afterthe core plating operation is completed, the whole core plane, array ormatrix is finished.

In order to produce an operative and commercially acceptable core memorydevice of this improved type, it was necessary to form a substrate and aprinted circuit formation thereon in a new and improved fashion to benot only receptive to the core formation but also to function therewith.Another hurdle overcome was that of so plating magnetic materialrelative to the printed circuit lines and of the effective square orrectangular hysteresis loop characteristics, so that driving current formemory controlling, sensing and writing purposes, when directed throughthe printed circuit lines, is effective for magnetic core switching.

Magnetic cores having rectangular hysteresis characteristics areemployed for memory purposes and are conventionally arranged in rows andcolumns with wire windings passing through the cores in each individualrow and in each individual column to be used for selection of aparticular core in a selected plane or group of planes by coincidentenergization of single column and row windings. Each single plane isprovided with a third winding comprising a sense winding that links eachcore of the plane in one or the other polarity sense or in alternatesense or with half the cores in one sense and half in the other sense soas to balance out the effects of those cores that are only partiallyexcited by one or the other winding during coincident energization of arow and column winding to select a particular core for interrogation. Ina three dimensional array, each plane of cores is also provided with afourth winding conventionally termed the inhibit winding that isselectively pulsed during a write interval to prevent the combinedeffects of the magnetomotive forces provided by the row and columnwindings from causing a change in remanence state of the core in thatplane when writing or rewriting information or binary characters in thearray. In an instance of application, like positioned cores in theseveral stacked two dimensional array planes, comprise bits of a binaryword and the similar row and column windings of each bit plane areseries connected so that on energization of these windings incoincidence, the core in each plane linked thereby would attain a onerepresenting remanence state unless inhibited by pulsing the fourthwinding individual to that plane.

Herctofore, magnetic core arrays of the type described have beenassembled manually with the windings threaded through the cores andproviding support therefor in the completed matrix. This means ofassembly has become increasingly time consuming and expensive sincearrays of greater capacity requiring a large number of cores are used,with the tendency being toward increasing bit capacity and use ofsmaller sized cores.

The present improvement contemplates an additive or plating processyielding printed circuit conductors and core windings wherein theassembly of a memory core array is produced rapidly and automatically inan economical high speed process. The method is based upon the use ofconductive and magnetic electrolytes in plating baths used in successionand between stop off resist pattern deposits to place patterns ofconductors and cores in proper succession on ceramic or plasticnonconductive substrates of unique formation. Although clad boards are apossibility it is also clear that an additive film of sprayed copper orother chemically deposited metal may be followed by subsequent build upby plating with copper, or other conductive material to form permanentconductor lines on the surface of the molded or cut plastic corereceiving plate or board. It is to be understood that such conductinglines on the board are present on both sides of the board and extend tothe edges of one or more sides of both faces of the board whereatterminal formations may be formed for reception of soldered or clampedlead wires, common vertical rods or bars, or other terminal formationswhich extend into machine proper for reception of the impulses whichcontrol the reading, writing and inhibiting controls over the corearray.

An object of the invention is to provide a method for assembling amagnetic core array obviating the need for threading wire conductorsthrough the cores by hand.

Another object of the invention is to provide an electroplating processfor formation of magnetic core arrays, said process being adapted forrapid automatic and economical operation of complete array fabrication.

Another object of the invention is to provide an improved method ofembodying printed circuit windings in a magnetic core matrix.

A further object of the invention is to provide a process combining thebest features of electrodeposition operation with additive printedcircuit techniques for the purpose of providing an improvedautomatically formed magnetic core matrix.

A still further object of the invention is the provision of a novel formof packaging involving the electroplating of electronic components insuch a fashion as to render them receptive to complete wiring andconnection by printed circuit techniques without need of any subsequentconnections by other operations.

Another object of the invention is to so control the plating of themagnetic material as to establish a very thin magnetic core coating andto further control so that the crystal formation of the structure ofsuch a coating is to be oriented to improve the characteristics formagnetic retentivity. It was found that by establishing a magnetic fieldin the plated core area while plating, the proper domain or crystalformation is established.

An object of the invention is the production of both magnetic corememory devices and the associated windings by means of additive printedcircuit processes.

Another object of the invention is the provision of a printed circuitboard so arranged as to be receptive to a memory device depositeddirectly thereon.

Another object of the invention is the provision of a method ofelectroplating an entire memory core array in a single operation.

A still further object of the invention is the provision of an articleof manufacture in the form of a perforated printed circuit boardcarrying a plurality of conductor lines so grouped as to be focused bythe board perforations and arranged there in narrow elongated nodulargroups for reception of memory material deposited in association wihsuch focused lines.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

In the drawings:

FIG. 1 is a plan view of an array of 16 plated cores formed on a printedcircuit board.

FIG. 2 is a reverse side plan view of the board of FIG. 1.

FIG. 3 is a sectional view taken along lines 33 in FIG. 1 and showing across section area of the board, the conductor lines thereon and thelayers of resin and magnetic material plated around the lines.

FIG. 4 is an enlarged detail view (partly in section) of a core arrayopened to show all films or layers of materials.

FIG. 5 is an oscillograph depiction of the magnetic loop hysteresischaracteristics of the cores of the invention.

FIG. 6 is a plan view of a board after successive steps of placingconductors thereon, an epoxy resin coat, a vacuum deposited layer ofcopper and a pattern of resist just prior to plating the core material.

FIG. 7 is a diagrammatic perspective view showing a number of cores inan array and the fashion in which the windings are directedtherethrough.

A single plane of a typical three dimensional array of magnetic core isshown in FIG. 7 where toroidal cores 26 are shown arranged in rows andcolumns, as aforementioned, and linked by column windings X and rowwindings Y. Such an array is illustrated, for example, in an articleentitled *Ferrites Speed Digital Computers by D. R. Brown and E.Albers-Schoenberg, appearing on page 146 of Electronics magazine, issuedApril i953, and described and claimed in the application of E. W. Bauerand M. K. Haynes, Serial No. 443,284, filed July 14, 1954, now PatentNo. 2,889,540, which application is assigned to a common assignee.

In such an arrangement a particular core is selected for reading by thesimultaneous energization of that X and that Y selection line or windingthat embraces that particular core. The current pulse on each lineprovides a magnetomotive force to each core that it links, which forceis less than the coercive force, and the single core energized by bothwindings then receives double the force. The selected core is thuscaused to change from a binary one representing remanence state to azero remanence state, if it held a binary one representation, and thisflux change develops an induced voltage in a sense winding S indicatingthis fact. If a zero remanence state had been stored in the interrogatedcore, little fiux change takes place and the sense Winding signal is oflow value so that storage of ones and zeros may be distinguished.Writing or storing a binary one state is similar to a reading operationbut with the sense of the X and Y drive pulses reversed to cause theselected core located at the winding intersection to change from a zeroremanence state to the one remanence state. This change also induces avoltage in the sense winding S but it is disregarded at write time bymeans of a gate (not shown). Writing a zero may be accomplished in a twodimensional array by failure to apply the X and Y Write direction pulsesin coincidence; and in a three dimensional array, where the X and Ylines link like positioned cores of plural planes to define words ofplural hits, the X and Y line pulses may he applied in coincidence buttheir effect counteracted in selected planes, where zeros are desired,by pulsing an inhibit winding Z in that bit plane. The X, Y, S and Zwindings are shown in FIG. 7 and it is to be noted that the inhibitwinding links all the cores in the same sense while the sense winding Slinks the cores in alternate diagonals in an opposite sense. The windingpattern of the sense winding as shown is such as to provide abidirectional output signal but, since those cores that are linked onlyby the selected X or selected Y Winding alone and are partially excitedcontribute some output signal on interrogation, the effects ofnon-selected cores tend to cancel one another. Many other sense Windingconfigurations are feasible wherein the half select signals arecouterbalanced, as for example the arrangement shown in FIG. 1, and theparticular form of array shown in FIG. 7 or FIG. 1 is not to beconsidered limiting with respect to the printed circuit assembly shownhereafter.

FIGS. 1 and 2 show both sides or faces 20 and 21 of a board, substrateor memory plane 22 which is molded, formed or cut square in shape andprovided with sixteen pairs of adjacent perforations 23 and 24. It isnoted that these sixteen pairs of perforations, openings or apertures23, 24 are arranged with regular spacing and aligned in horizontal rowsand vertical columns of a 4 x 4 matrix or array.

Between each pair of openings 2324 there is a narrow strip or grid areaof board material 25 which constitutes a memory module and bears thering of magnetic core material 26 under which is a thin copper film (achemical or vacuum metallized deposit of about .000010 inch) and anepoxy resin coat 27 (FIG. 3) and then the conductors 28 over an adhesiveon the board. Wider areas or strips 19 and 29 are between openings 23,24 which are not of a pair and provide strength and room for conductorconnection paths. It is contemplated that many or all unrelatedadjoining perforations could be made as one to condense the boardfurther and eliminate punches or fabrication (i.e., three openings couldhave two cores on the intervening strip).

As seen in FIG. 1 the X conductor lines 28 as core write or selectionbias lines or windings, are of a form or path which winds more or lessdirectly across the board 22. For example, line XlXl at the left is seento wind in and out through the four cores of the left column. In asimilar fashion, all four X lines X1X4 are seen to follow a generallyvertical path across the board and through the related cores of columnsone to four.

On the opposite face 21 of board 22 (FIG. 2) the Y selection or biaslines 31 are seen to have rather direct horizontal paths, each throughfour cores 26 of a horizontal row. Widened terminal tabs 32 are at theboard edges just as the X line tabs 34 are near the other edges.

In FIG. 2 an inhibit Z line 35 is seen to originate at tab 36, cross tothe right through four cores and then cross back to the left through thesecond horizontal row of cores before going through hole 37 to the otherside of the board. In FIG. 1 it is noted that Z line 35 appears betweenholes 37 and 38. On FIG. 2 the Z line 35 reappears at hole 38 and windsacross to the right and back to terminal 39.

The two sense or read bias lines 40, FIG. 1, are seen to have tortuouspaths between terminals 4142 and 43- 44. If the start is assumed at tab43, a sense winding 40 is seen to pass zigzag through the two lowercores of the third column, then diagonally upward and to the rightthrough the two upper cores of the fourth column, before descendingthrough the two upper cores of the third column, passing through hole46, reappearing at hole 47, and finally winding through the lower twocores of the fourth column and ending at tab 44. The other sense winding40 at the left between tabs 41 and 42 follows a similar path through thefirst two columns of cores.

It is important to note that all four types of windings have beenarranged through the cores without any of the windings crossing theirown or any other winding. Although it is possible for printed circuitlines to be deposited or crossed over other previously arranged lines,it is much simpler and more economical to deposit all lines at once inone layer on each side of the board.

Before outlining the gist of the artwork technique, it is well to notethe shapes of the various coatings or layers as shown in FIG. 6, inaddition to the printed conductor lines 28, 31, 35 and 40 already notedwith respect to FIGS. 1 and 2. Although FIG. 6 is shown with the board22 in its finished outline of square shape and formations of onlysixteen pairs of holes 23, 24 it is to be realized that other breakawayboard extensions and locating holes may be provided to aid inregistration of the various patterns of stencils and resists.

After the printed circuit lines and terminal tabs are placed on bothfaces of the board, thin coats of an epoxy resin or anotherthermoplastic or thermosetting plastic or varnish are applied in theshape 49, mainly to coat the conductors in the areas where theelectroplated NiFe is to be superimposed later. Over the epoxy coatthere is added a thin film of adhesive which is the undercoat for a filmof copper. Over the epoxy and adhesive coat 49 there is applied a vacuumdeposited film 50 of copper about .000010 in thickness and extending toat least one board edge. This copper film 50 is to form a receptiveundercoat for the magnetic NiFe and also provide a conductive layer atthe board edge for terminal clamps to electrically connect the board asthe receiving cathode in the electrolyte for the NiFe plating. Sincethere is to be at least one winding through each core conducting acurrent to cause a magnetic orienting field at each core area at thesame time as the electroplating of NiFe,.it is necessary to keep thewindings and the copper film 50 insulated, and that is what is done bythe epoxy coat 49.

In order to limit the NiFe core deposits to the restricted cylindricalareas, a resist coating 51 is applied to all the board except whereterminals are to grasp tabs, the edges of copper coat 50, and the areasfor the cores 26. The stippled areas in FIG. 6 represent the resistcoated areas before NiFe plating. There are two ways in which the resistcoat may be applied near the core areas 26; it may or may not cover thethree side walls of the openings 23 and 24 away from the core area. Ifthe resist is applied to the opening walls, then there is no extraneousNiFe deposits outside the core area. However, if resist 51 is onlyapplied to the faces of board 22, then a shearing die removal, or otheredge cutting, grinding or filing etc., operation is required to removedeposits outside the cylindrical core area.

It is to be understood that the showings in the drawings FIGS. 1-4 arenecessarily out of proportion because they are for illustrative purposesso that strip 25 could be actually of a more elongated form with alength about 3 or 4 times its width. The deposits and platingthicknesses of FIG. 3 are also merely illustrative and the ranges ofdimensions areto be noted as given here.

Board thickness of about .03 1-.062 inch Conductor thickness, .0005 to.0015

Conductor width, about .010 and .010 spacing Insulator coating such asepoxy resin coat. about .001

Plated magnetic core, about .002 to .00025 Percent iron in plating, 25to iron and to 3 nickel Core diameter, .040 to .060, somewhat square orrectangular Core length, .125 to .187

Board of 4 x 4 cores, 2% square Of course, the foregoing figures areexamples only and not to be regarded as limitations. as it is realizedthat many variations may be made without departing from the spirit ofthe invention.

First, the steps of entire general artwork techniques may be stated.Then this may be followed by an example of an additive printed circuitmethod. Finally, examples of magnetic material plating baths andprocedures are to be presented.

The general artwork techniques:

(1) Startuse glass or ceramic base material with core holes andconductor grooves pre-molded.

(2) Metallize base as with vacuum or chemically deposited copper.

(3) Mask by photo resist and collimated light leaving conductor areasuncoated.

(4) Electroplate conductor lines with copper.

(5) Remove masking ink and background copper film.

(6) Apply insulating coating to board. Dry.

(7) Metallize the board.

(8) Mask with photo resist and collimated light, coating all surfaceareas except desired core areas.

(9) Electroplate core areas with nickel-iron. During plating, conductorlines carry current to generate an orienting magnetic field for thedepositing core material.

(10) Remove photo resist.

Another technique is as follows:

(1) Start with a double clad epoxy paper (or any stable ceramic likestock).

(2) Punch registration holes (mold or form in the case of a ceramic).

(3) Punch through holes (molded in the case of glass or ceramic).

(4) Metallize card, copper chemical or vacuum metallizing on board andthrough the holes.

(5) Negative pattern of resist for conductors.

(6) Plate conductors and throughholes.

(7) Remove resist.

(8) Punch core holes.

(9) Etch card.

(10) Apply epoxy insulating coating.

(11) Dip in very thin adhesive Armstrong Nl78,

bake.

2 metallizing steps 2 screening steps 2 plating steps As an example of amethod of forming the underlying printed circuit conductors or corewinding lines of the present invention, the following p ocedures may befollowed.

(1) Start with an unclad board.

(2) Cut the board to size and punch holes large enough for terminals.

(3) Clean the board with a solvent such as methyl ethyl ketone.

(4) Spray an adhesive on both sides and inside holes- Armstrong N-l78.

(5) Dry adhesive in an oven, one-half hour at 200 F.

(6) Vacuum metallize with copper film while board is rotating. Entireboard is coated with copper film of a thickness approximately 0.000005of an inch.

(7) Silk screen a negative of the desired pattern on the board,Resist-Photocircuits K2.

(8) Copper electroplate the board to a conductor thickness of about0.0015 of an inch, between resist areas,

there being at times a progressively low and high current densityplating in the same bath.

(9) Remove resist as by degreasing.

(10) Remove background of vacuum deposit copper film and adhesive bychromic and sulphuric acid etching compound with a scrubbing actionwhich is mainly to remove the adhesive. The background copper film ischemically dissolved by the etch solution and the scrubbing action isused to facilitate removal of. the adhesive by the etch. The relativelythick conductor lines are etched to a slight extent which does notimpair their eventual use. It is estimated that the copper film is takenoff in three seconds and the scrubbing requires two minutes.

(ll) Cure remaining adhesive under conductor lines and through holes bybaking for one-half hour at 330 F.

From this point on the core plating steps are started.

In addition to the foregoing steps, there are several intermediaterinsing operations.

As alternatives to the etched or additive processes noted hereinbefore,the printed conductors could be formed by a stamped/molded process asset forth in the expired Patent 2,427,144. However, for small corearrays and wherever the conductors are to be thin and close together,the etched process may be preferred.

Magnetic materials having square hysteresis loops have hitherto beenfound of value in various fields, such as the field of mechanicalrectification of alternating current and the field of magneticamplification. Hysteresis loop tests using direct current testingequipment are well known. A material is said to have a square hysteresisloop if, in such tests, it exhibits a high ratio of residual induction(Br) to maximum induction (Bm). The Br/Bm ratio for a given material isnot a single value, but varies with the peak magnetizing force andpasses through a maximum as saturation is approached. While the termssquare or rectangular as applied to hysteresis loops may be susceptibleof wide interpretation, the materials to which this invention isaddressed have greater utility the higher the maximum Br/Bm ratiobecomes; and in general contemplate materials having Br/Bm ratio ofabout 0.90.

High speed digital computing machines have been built using electronicvacuum tubes. While such machines are capable of solving problems ofprodigious length and complexity, a serious disadvantage is to be foundin the possibility of unpredictable tube failure, making recheckingimpossible even though an error is known. The advent of grain orientednickel-iron alloys characterized by rectangular hysteresis loopsprovides the possibility of using magnetic cores to replace electronictubes in the memory units of such computers.

Recent developments in digital computers as well as other electronicdevices have necessitated higher rates of magnetization or shorterswitching times within the cores than were possible with previouslyavailable magnetic all] devices. .Since increasing the rate ofmagnetization is dependent upon reducing eddy currents, holding themagnetic films to thinner gauges would seem to be indicated. Thedifiiculty is that in materials previously known, in which rectangularloops could be produced for this purpose, such as grain oriented 3%silicon-iron and grain oriented 48% nickel-iron, the coercive forceincreases rapidly with decreasing thickness and becomes excessive at theultra-thin gauges required. Any increase in coercive force isundesirable, since it necessitates an increase in the exciting current,which may exceed that available.

P10. 5 shows a typical rectangular hysteresis loop of thecharacteristics produced under the conditions of plating NiFe cores on aprinted circuit board as outlined herein. The squareness ratio of theloop was found to be good and in the range of .8 to 1. The appliedplating current was about 20 A. per square foot of toroidal core areafor a time of plating of about 12 minutes. At the same time an orientingmagnetic field was applied through core windings at about 2.5 A. for thesame period as the plating time. The temperature of the electrolyte washeld in the vicinity of 74 F. and a pH of 2.8 to 3.

One electrolyte solution may be given here as an example:

Solution composition:

194 g./1NiCl '6H O(50 g./1Ni) 5.7 g./1FeCl '4H O (1.6 g./1Fe) 9.7g./1NaCl 25.0 g./1H BO 0.83 g./1 saccharin 0.42 g/l sodium laurylsulfate Solution preparation: The nickel chloride, ferrous chloride.sodium chloride and boric acid were dissolved in distilled water. Thesolution was treated with activated carbon and filtered. Afterfiltration the saccharin and sodium lauryl sulfate were added. The pHwas lowered with HCl to 2.73.0. All salts used were reagent or U.S.P.grade.

Fluoborate bath:

284 cc./l nickel fluoborate concentrate 9.6 cc./1 ferrous fiuoborateconcentrate 0.83 g./l saccharin Sulfate bath:

218 g./1NiSO -6H O 11.2 g./lFeSo (NH )2SO.,-6H O g./lH BO 0.83 g./1saccharin 0.42 g./1 sodium lauryl sulfate Chloride bath:

194 g./1NiCl 6H O 5.7 g./lFeCl -4H O 9.7 g./ lNaCl 0.83 g./1 saccharin0.42 g./1 sodium lauryl sulfate Chloride-sulfate bath:

218 g./lNiSO -6H O 11.2 g./1FeSO (NH.;)2SO -6H O g./1NaCl 25.0 g./lH BO0.83 g./1 saccharin 0.42 g./1 sodium lauryl sulfate Magnetic field: Theapplication of a circumferentially directed magnetic field whileelectroplating has a pronounced effect in squaring the resultanthysteresis loop of the test bit. This is due to alignment of domains inany easy direction during deposition. Bits were plated up to or at 20oersted average strength magnetic fields. At about 5 oersteds resultswere good for particular proportions of core deposited. For other sizes,field density which may be used for the present purpose, note was FIG. 5shows effect of composition on He, Br and Br/Brn respectively. MinimumHe was obtained at a plate composition of about 26% iron.

In order to electroplate the NiFe magnetic coating, which is only one ofa variety of such magnetic materials which may be used for the presentpurpose, note was taken of the above number of solutions or baths whichwere found effective and suitable for illustrative purposes. It was alsofound that by using the following electrolyte solution, a magnetic coremay be formed by depositing a coating of about .00025 inch thickness ona film of copper over an epoxy resin of about .001 thickness overprinted circuit lines which are of heavier copper. The following arethree examples of the electrolytes used.

115 F., pH 2.52.7. Iron anode or combination NiFe anode.

50 grams per liter of nickel as nickel fiuoborate solution 10 grams perliter of MgCl 1 gram per liter of saccharine (sic) (soluble) l to 1.9grams per liter of iron as ferrous fiuoborate solution Sample platingswere made from the above solutions (four iron concentrations of 1.0,1.3, 1.6 and 1.9 grams per liter of iron) and analyses were made.

Analyses were as follows:

Iron content Nickel corn in Solution, tent in Plate.

grams per percent liter The plating conditions above were, 120 F.,pH:2.2 (raised the small pH of nickel fluoborate with NiCO 20 amps persq. fL the cathode current density. Separate anodes used were ofdifferent metal (80% nickel and 20% iron). The plate thickness about0.001 inch.

In order that preferred magnetic behavior may be obtained, the nickeliron alloy should have orientations which are favorable formagnetization. Under ordinary plating conditions, the thin magneticcoating would have random crystal formation and failure to be suited forthe best results in use as magnetic switching devices.

In the process of plating according to the present invention, theunderlying conductor lines of the plated circuit are to be madeconductive during plating to create a magnetic field which makes itspresence felt in the area or cylindrical formation upon which themagnetic material is being plated. Under such specially arrangedconditions of electrolysis a nickel core board can be produced withbetter magnetic properties because the thin layer has a highly preferredcrystal orientation with the (111) plane parallel to the surface. Thispreferred orientation is sought in order to realize the best magneticproperties sought for magnetic core memory devices.

Heretofore, it was thought that preferred orientation could be realizedonly in extremely thin formations of magnetic material, however, theless desirable directions of growth are avoided in the present instanceand an approach or attainment of the preferred orientation is realizedin the instance of plating as outlined herein with the magnetic fieldbeing in effect during the operation.

Although heretofore it was believed that magnetic plating with goodcharacteristics could be produced only by the use of uniform and limitedbase material upon which the coating was deposited in the presentinstance, it will be noted to the contrary, that the plating, althoughit is continuous over various metallic and resinous background material.it is still effective as a magnetic switching device.

Another departure from the prior art is found in the comparatively widerange of electrolyte pH and the current density now used but which wasthought critical in order to produce preferred orientation. Now with theuse of metallic control. it is found the deposition of magnetic materialin the preferred plane is obtained without having the depositionprocedures held with impractical tolerances.

In accordance with the recited mode of depositing metallic material theorientation is such that a crystal axis appears at right angles to thesurface parallel to the direc tion of current. From this it is apparentthat the formed core material will be magnetized rapidly and assume aswitched condition in an unusual fashion.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing front the spirit andscope of the invention.

What is claimed is:

1. A magnetic storage matrix comprising:

a flat nonconductive substrate with a grid of separate memory areasformed by rows and columns of closely spaced pairs of slot openings,there being between each pair of openings a separate memory area stripreceptive to cylindrical deposits.

a plurality of sets of printed conductors on said substrate withconductors of different sets grouped over each of said strips in amemory area,

and cylindrical thin films of magnetic material deposited on saidseparate strips over said conductors as separate memory elements, saidmaterial being of a nature exhibiting square loop hysteresischaracteristics.

2. An automated magnetic core memory array comprising:

a square fiat sheet of insulation with regularly spaced and aligned rowsand columns of narrow elongated strips of insulation between pairs ofadjacent related slot openings, there being larger connective insulationareas other than said strips between unrelated slots,

said sheet bearing on both faces a plurality of sets of printed circuitlines which run in groups across both faces of said elongated strips andend with enlarged terminal areas at the edges of said sheet. each groupon a strip including lines of all different sets of lines,

a coat of plastic on said array, cylindrical films of pre liminarynonmagnetic metal on said plastic coated strips,

and outer magnetic core films restricted to deposits encircling saidclongated strips with a nickel-iron composition having magnetic squareloop hysteresis characteristics.

3. A magnetic remancncc device comprising a mounting member in the formof a substrate sheet of electricalIy insulating material with aplurality of through apertures extending between opposed faces thereof,an electrically conductive coating over said mounting member arranged todefine a current path therealong, and a magnetic coating extendingcircumferentfally about said mounting member and surrounding saidcurrent path for clectmmag nctic linking therewith.

4. A magnetic remanence device comprising a mounting member in the formof a substrate sheet of clcctrically insulating material with aplurality of through apertures extending between opposed faces thereof,electrically conductive coatings over said mounting member arranged todefine current paths therealong, a coating of electrically insulatingmaterial over said conductive coatings, and a magnetic coating extendingcircunzferentially about said mounting member and surrounding saidcurrent paths for electromagnetic linking therewith.

5. A memory plane COIHPI'iSiHg a substrate sheet formed with a pluralityof through apertures extending between opposite faces thereof, and beingso arranged and spaced from each other that the portions of saidsubstrate sheet between repsective neighboring side walls thereof forman array of mounting members each having opposite ends joined to theremainder of said substrate sheet and a circumferential girth defined bysaid opposite substrate sheet faces and said neighboring aperture sidewalls, electrically conductive means traversing said mounting members ina manner to define current paths extending from one of said oppositeends thereof to the other, and a magnetic coating surrounding theassemblies of said mounting members and said conducting means andextending along said opposite substrate sheet faces and said neighboringaperture side walls about the girth of individual mounting members forelectromagnetic linking with said current paths.

6. A memory plane comprising a substrate sheet of electricallyinsulating material formed with a plurality of through aperturesextending between opposite faces thereof. said apertures having sidewalls and being so arranged and spaced from each other that the portionsof said substrate sheet between respective neighboring side wallsthereof form an array of mounting members each having opposite endsjoined to the remainder of said substrate sheet and a circumferentialgirth defined by said opposite substrate sheet faces and saidneighboring aperture side walls, alternate electrically conductive andelectrically insulating coatings over said substrate sheet arranged toform a plurality of conductor strips, covered over by said insulatingcoatings, said conductor strips traversing said mounting members in amanner to define current paths extending from one of said opposite endsthereof to the other, and a magnetic coating surrounding the assembliesof said mounting members and said conducting and insulating coating andextending along said opposite substrate sheet faces and said neighboringaperture side walls about the girth of individual mounting members forelectromagnetic linking with said current paths.

7. A memory plane comprising a substrate sheet of electricallyinsulating material formed with a plurality of through aperturesextending between opposite faces thereof, said apertures having sidewalls and being so arranged and spaced from each other that the portionsof said substrate sheet between respective neighboring side wallsthereof form an array of mounting members each having opposite endsjoined to the renminder of said substrate sheet and a circumferentialgirth defined by said opposite substrate sheet faces and saidneighboring aperture side walls, alternate electrically conductive andelectrically insulating coatings over said substrate sheet arranged toform a plurality of conductor strips covered over by said insulatingcoatings, said conductor strips traversing said mounting member array ina manner to define respective current paths extending along respectiverows of mounting members, the mounting members of respective rows beingtraversed by said current paths from one of said opposite ends thereofto the other said conductor strips being arranged in coordinate groupslocated on said opposite substrate sheet faces for electrical insulationfrom each other, the respective directions of traverse of said conductorstrips being parallel within each coordinate group and mutuallytransverse between said coordinate groups so that each crossing of anyconductor strips of different coordinate groups uniquely defines anaddress in said mounting member array and a magnetic coating surroundingthe assemblies of said mounting members and said conducting andinsulating coating and extending along said opposite substrate sheetfaces and said neighboring aperture side walls about the girth ofindividual mounting members for electromagnetic linking with saidcurrent paths.

8. A memory plane comprising a substrate sheet of electricallyinsulating material formed with a plurality of through aperturesextending between opposite faces thereof said apertures having sidewalls and being so arranged and spaced from each other that the portionsof said substrate sheet between respective neighboring side wallsthereof form an array of mounting members arranged in mutuallytransverse columns and each having opposite ends joined to the remainderof said substrate sheet and a circumferential girth defined by saidopposite substrate sheet faces and said neighboring aperture side walls,alternate electrically conductive and electrically insulating coatingsover said substrate sheet arranged to form a plurality of conductorstrips covered over by said insulating coatings, said conductor stripstraversing said mounting member array in a manner to define respectivecurrent paths extending along respective rows of mounting memberstransverse to said columns thereof, the mourning members of respectiverows being traversed by said current paths from one of said oppositeends thereof to the other, said conductor strips being arranged incoordinate groups located on said opposite substrate sheet faces forelectrical insulation from each other, the respective directions oftraverse of said conductor strips being parallel within each coordinategroup and mutually transverse between said coordinate groups so thateach crossing of any conductor strips of different coordinate groupsuniquely defines an address in said mounting member array, and amagnetic coating surrounding the assenzblies of said mounting membersand said conducting and insulating coating and extending along saidopposite substrate sheet faces and said neighboring aperture side wallsabout the girth of individual mounting members for electromagneticlinking with said current paths.

9. A memory plane comprising a substrate sheet of electricallyinsulating material formed with a plurality of through openingsextending between opposite faces thereof including a group of aperturesand a connecting bore each having side walls, said apertures being soarranged and spaced from each other that the portions of said substratesheet between respective neighboring side walls thereof form an array ofmounting members each having opposite ends joined to the remainder ofsaid substrate sheet and a circumferential girth defined by saidopposite substrate sheet faces and said neighboring aperture side walls,alternate electrically conductive and electrically insulating coatingsover said substrate sheet arranged to form a conductor strip coveredover by said insulating coatings, said conductor strip traversing saidmounting members in a manner to define current paths extending from oneof said opposite ends thereof to the other and including segments onsaid opposite substrate sheet faces interconnected along said connectingbore side walls and each traversing a share of said conductor striptraversing said mounting members in a manner to define current pathsextending from one of said opposite ends thereof to the other andincluding segments on said opposite substrate sheet faces interconnectedalong said connecting bore side walls and each traversing a share ofsaid mounting members and a magnetic coating surrounding the assembliesof said mounting members and said conducting and insulating coating andextending along said opposite substrate sheet faces and said neighboringaperture side walls about the girth of individual mounting members forelectromagnetic linking with said current paths.

]0. A memory plane comprising a substrate sheet of electricallyinsulating material formed with a plurality of through aperturesextending between opposite faces thereof, said apertures having sidewalls and being so arranged and spaced from each other that the portionsof said substrate sheet between respective neighboring side wallsthereof form an array of mounting members each having opposite endsjoined to the remainder of said substt ate sheet and a circumferentialgirth defined by said opposite substrate sheet faces and saidneighboring aperture side walls, alternately electrically conductive andelectically insulating coatings over said substrate sheet arranged toform a plurality of sets of conductor strips arranged in overlyingrelationship and interleaved with and covered over by said insulatingcoatings, said conductor strips traversing said mounting members in amanner to define current paths extending from one of said opposite endsthereof to the other, and a magnetic coating surrounding the assembliesof said mounting member and said conducting and insulating coating andextending along said opposite substrate sheet faces and said neighboringaperture side walls about the girth of individual mounting members forelectromagnetic linking with said current paths.

1]. A memory plane comprising a substrate sheet of electricallyinsulating material formed with a plurality of through openingsextending between opposite faces thereof including a group of aperturesand a connecting bore each having side walls, said apertures being soarranged and spaced from each other that the portions of said substratesheet between respective neighboring side walls thereof form an array ofmounting members arranged in mutually transverse columns and each havingopposite ends joined to the remainder of said substrate sheet and acircumferential girth defined by said opposite substrate sheet faces andsaid neighboring aperture side walls, alternate electrically conductiveand electrically insulating coatings over said substrate sheet arrangedto form a plurality of sets of conductor strips arranged in overlyingrelationship and interleaved with and covered over by said insulatingcoatings, said sets including a set of first conductor strips and atleast one further conductor strip set, said first conductor stripstraversing said mounting member array in a manner to define respectivecurrent paths extending along respective rows of mounting memberstransverse to said columns thereof, the mounting members of respectiverows being traversed by said current paths from one of said oppositeends thereof to the other, said first conductor strips being arranged incoordinate groups located on said opposite substrate sheet faces forelectrical insulation from each other, the respective directions oftraverse of said first conductor strips being parallel within eachcoordinate group and mutually transverse between said coordinate groupsso that each crossing of any first conductor strips of differentcoordinate groups uniquely defines an address in said mounting memberarray, said further conductor strip set including a second conductorstrip traversing said mouting members in a manner to define currentpaths extending from one of said opposite ends thereof to the other andincluding segments on said opposite substrate sheet faces interconnectedalong said connecting bore side walls and each traversing a share ofsaid mounting members, and a magnetic coating surrounding the assembliesof said mounting members and said conducting and insulating coating andextending along said opposite substrate sheet faces and said neighboringaperture side walls about the girth of individual mounting members forelectromagnetic linking with said current paths.

References Cited The following references, cited by the Examiner, are ofrecord in the patented file of this patent or the original patent.

OTHER REFERENCES A Compact Coincident-Current Memory, A. V. Pohm, S. M.Rubens, Proceedings of the Eastern Joint Computer Conference, Dec. 1042,1956, pp. -123.

BERNARD KONICK, Primary Examiner G. M. HOFFMAN, Assistant Examiner U.S.Cl. X.R. 29-609

